The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in the present disclosure and are not admitted to be prior art by inclusion in this section.
Voltage-mode high-speed input/output (HSIO) transmitters typically include an array of driver bit-slices to drive a data signal on one or more transmission lines. Such transmitters provide programmable output impedance by enabling or disabling certain driver bit-slices. Accordingly, the output impedance may be adjusted to compensate for process, voltage, and temperature (PVT) variation to meet the impedance specification of the input/output link. However, the typical architectures for HSIO transmitters suffer from several drawbacks, such as a large pad capacitance (Cpad), high power dissipation, and impedance compensation and de-emphasis operations that are coupled together (e.g., one affects operation of the other).